JPH0187552U - - Google Patents
Info
- Publication number
- JPH0187552U JPH0187552U JP1987183042U JP18304287U JPH0187552U JP H0187552 U JPH0187552 U JP H0187552U JP 1987183042 U JP1987183042 U JP 1987183042U JP 18304287 U JP18304287 U JP 18304287U JP H0187552 U JPH0187552 U JP H0187552U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- fin
- fins
- cooling structure
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987183042U JPH0525244Y2 (en]) | 1987-12-01 | 1987-12-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987183042U JPH0525244Y2 (en]) | 1987-12-01 | 1987-12-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0187552U true JPH0187552U (en]) | 1989-06-09 |
| JPH0525244Y2 JPH0525244Y2 (en]) | 1993-06-25 |
Family
ID=31474475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987183042U Expired - Lifetime JPH0525244Y2 (en]) | 1987-12-01 | 1987-12-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0525244Y2 (en]) |
-
1987
- 1987-12-01 JP JP1987183042U patent/JPH0525244Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0525244Y2 (en]) | 1993-06-25 |
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